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20140919Notes

Where we are right now:

• Dreamer goes through synthesis and P&R using modified reference-chip flow
• suggestion: tape-out simple RTL = existing RTL (dreamer, not hurricane)
  • need to get verification/simulation working
  • can simulate single core but can’t completely simulate interface and array of cores
  • Chisel tester connects to another Chisel tester for the desired use, and this connection is not fully fleshed out
  • current testing structure: assume Chisel tester is ground truth and diff VCD dumps
  • desired: suite of benchmarks or regression tests to get full coverage on Chisel/Verilog results
  • idea: use Chisel torture test

Tape-out requirements:

1. need static RTL to get a tape-in flow finished (use finished Dreamer RTL)
2. need Verilog testbench to verify functionality
3. need existing Dreamer flow to modify for new technology
4. need technology
5. need to decide on an array size to tape-out
6. need to decide on an interface with outside world