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- LVDS questions:
- clocking? ready/valid interface? synchronization? what do we have right now?
- pass clock in with data
- 1GHz hard to synchronize on the board, so probably this is maximum value
- talk to an expert here (can we get IP?)
- correlator numbers:
- good! use as test case for now, assume 1Gb/s minimum input data rate and scale up as much as we can
- testing:
- Palmer will get Stevo a testbench I can use to test synthesis/PAR results soon
- need to get PT up and running to get accurate power numbers from these activity factors
- bora’s thoughts:
- memory is still open question
- currently a scratchpad, but we’re probably memory-limited in algorithms
- communication between tiles and memory
- families of chips - different ones which work well for different kernel types
- add other benchmarks (beyond correlator) and make sure they fit on memory (or we need something else for memory, i.e. Rocket)
- SHA3 or other hashing algorithm
- other radio astronomy kernels
- viterbi/LDPC/Turbo
- MIMO matrix decoder (Antonio and Simon)
- Bora will look at papers by Alcatel Lucent and Cisco re: network chips
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