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20141203Notes

1) Spatial computing research overlap with Krste

     - need coordination with RISC-V since we’re using it
     - use LTE decoder from CS250 project as use-case

2) New architecture overview

     - largely same as DREAMER, but with Rocket core (RISC-V ISA) for easier programming
     - tile has Rocket plus ROCC accel. for networking
     - temporarily include a big memory inside each tile for HTIF communication
     - however instead we’ll use a shared-memory structure, but with really slow shared memory
          - I$ is easy, doesn’t need coherency, just crossbar connection to separate Rocket running Linux
          - D$ will not store remote addresses, so not really a cache, like NUMA (non-uniform memory array), but rather a bunch of distributed “caches” on tiles and a large memory off-chip

3) Retreat talk

     - proposing this new architecture to get feedback
     - differentiating it from other architectures
     - propose computation kernels and ask for feedback/other kernels to test

4) Tape-out meeting schedule change (this week only): 3-5pm, ASPIRE Lab